Compuertas y Circuitos
1_ Para las compuertas AND,OR y XOR de 2,3 y 4 Entradas dar :
Función _ Símbolo _ Tabla de Verdad
Función Y (AND):
2 entradas
2 entradas
F = A · B ( · : Se lee Y )
Tabla de Verdad
A
|
B
|
F
|
0
|
0
|
0
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
1
|
3entradas
F = A · B · C
Tabla de verdad
4 entradas
F = A · B · C · D
Tabla de verdad
Función Ó (OR):
2 entradas
A
|
B
|
C
|
F
|
0
|
0
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0
|
0
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0
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0
|
1
|
0
|
0
|
1
|
0
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
1
|
1
|
4 entradas
F = A · B · C · D
Tabla de verdad
A
|
B
|
C
|
D
|
F
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
0
|
0
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0
|
1
|
0
|
1
|
0
|
0
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1
|
1
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0
|
0
|
0
|
1
|
1
|
1
|
0
|
1
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0
|
0
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0
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0
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1
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0
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0
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1
|
0
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1
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0
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1
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0
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0
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1
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0
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1
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1
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0
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1
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1
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0
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0
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0
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1
|
1
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0
|
1
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0
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1
|
1
|
1
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0
|
0
|
1
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1
|
1
|
1
|
1
|
Función Ó (OR):
2 entradas
F = A + B ( + : Se lee Ó )
Tabla de Verdad
A
|
B
|
F
|
0
|
0
|
0
|
0
|
1
|
1
|
1
|
0
|
1
|
1
|
1
|
1
|
3 entradas
F = A + B + C
Tabla de verdad
A
|
B
|
C
|
F
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
1
|
0
|
0
|
1
|
1
|
0
|
1
|
1
|
1
|
1
|
0
|
1
|
1
|
1
|
1
|
1
|
4 entradas
F = A + B + C + D
Tabla de verdad
A
|
B
|
C
|
D
|
F
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
1
|
0
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
0
|
1
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
1
|
1
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
1
|
0
|
1
|
0
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1
|
1
|
0
|
1
|
1
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1
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1
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1
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0
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0
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1
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1
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1
|
0
|
1
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1
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1
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1
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1
|
0
|
1
|
1
|
1
|
1
|
1
|
1
|
Operación ó Exclusiva (XOR):
2 entradas
( 
: Se lee Ó Exclusivo )
Tabla de Verdad
A
|
B
|
F
|
0
|
0
|
0
|
0
|
1
|
1
|
1
|
0
|
1
|
1
|
1
|
0
|
3 entradas
F = A
B C
Tabla de verdad
A
|
B
|
C
|
F
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
1
|
1
|
4 entradas
F = A
B C D
Tabla de verdad
A
|
B
|
C
|
D
|
F
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
0
|
0
|
1
|
1
|
1
|
1
|
1
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0
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
0
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1
|
1
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1
|
1
|
1
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0
|
0
|
0
|
1
|
1
|
0
|
1
|
0
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1
|
1
|
1
|
0
|
1
|
1
|
1
|
1
|
1
|
0
|
2_Para el Inversor dar :
Función _ Símbolo _ Tabla de Verdad
Función Nó (NOT) - (Inversora-Complemento-Negación):
F = A
Tabla de Verdad
A
|
F=A
|
0
|
1
|
1
|
0
|
3_ Para el siguiente circuito indicar el estado de la variable en cada punto :
4_Para las compuertas NAND,NOR y XNOR de 3 Entradas dar :
Función _ Símbolo _ Tabla de Verdad
No-Y (NAND GATE):
 |
Tabla de Verdad
A
|
B
|
C
|
F
|
0
|
0
|
0
|
1
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
1
|
1
|
0
|
0
|
1
|
1
|
0
|
1
|
1
|
1
|
1
|
0
|
1
|
1
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1
|
1
|
0
|
No-O (NOR GATE):
Tabla de Verdad
A
|
B
|
C
|
F
|
0
|
0
|
0
|
1
|
0
|
0
|
1
|
0
|
0
|
1
|
0
|
0
|
0
|
1
|
1
|
0
|
1
|
0
|
0
|
0
|
1
|
0
|
1
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
1
|
0
|
No ó Exclusiva (X NOR GATE):
A
|
B
|
C
|
F
|
0
|
0
|
0
|
1
|
0
|
0
|
1
|
0
|
0
|
1
|
0
|
0
|
0
|
1
|
1
|
1
|
1
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0
|
0
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0
|
1
|
0
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1
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1
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1
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1
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0
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1
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1
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1
|
1
|
0
|
5_ Los siguientes trenes de pulsos están aplicando a compuertas AND,OR y XOR. De tres Entradas. Dibujar la Salida de c/u.
A
|
0
|
1
|
0
|
0
|
1
|
0
|
1
|
1
|
1
|
0
|
0
|
|||
B
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
|||
C
|
0
|
1
|
0
|
0
|
1
|
0
|
1
|
0
|
0
|
1
|
0
|
|||
AND
|
0
|
1
|
0
|
0
|
0
|
0
|
1
|
0
|
0
|
0
|
0
|
|||
OR
|
0
|
1
|
1
|
0
|
1
|
1
|
1
|
1
|
1
|
1
|
1
|
|||
XOR
|
0
|
1
|
1
|
0
|
0
|
1
|
1
|
1
|
1
|
0
|
0
|
|||
6_Buscar y Pegar el PIN-OUT de todos los Circuitos Integrados (TTL y CMOS) que contengan únicamente compuertas e inversores.
CMOS
- Quad 2-input gates
- 4001 quad 2-input NOR
- 4011 quad 2-input NAND
- 4030 quad 2-input EX-OR (now obsolete)
- 4070 quad 2-input EX-OR
- 4071 quad 2-input OR
- 4077 quad 2-input EX-NOR
- 4081 quad 2-input AND
- Triple 3-input gates
- 4023 triple 3-input NAND
- 4025 triple 3-input NOR
- 4073 triple 3-input AND
- 4075 triple 3-input OR
- Dual 4-input gates
- 4002 dual 4-input NOR
- 4012 dual 4-input NAND
- 4072 dual 4-input OR
- 4082 dual 4-input AND
TTL
- Quad 2-input gates
- 7400 quad 2-input NAND
- 7403 quad 2-input NAND with open collector outputs
- 7408 quad 2-input AND
- 7409 quad 2-input AND with open collector outputs
- 7432 quad 2-input OR
- 7486 quad 2-input EX-OR
- 74132 quad 2-input NAND with Schmitt trigger inputs.
- Triple 3-input gates
- 7410 triple 3-input NAND
- 7411 triple 3-input AND
- 7412 triple 3-input NAND with open collector outputs
- 7427 triple 3-input NOR
- Dual 4-input gates
- 7420 dual 4-input NAND
- 7421 dual 4-input AND
7_Para los siguientes circuitos dar la función y la Tabla de Verdad.
Tabla de verdad
Tabla de verdad
Tabla de verdad
Tabla de verdad
8_ Completar las siguientes identidades. Justificar mediante tabla de verdad. Dibujar los circuitos
A+A= A
A + 0 = A
A + 1 = 1
A . A = A
A . 0 = 0
A . 1 = A
9 _Verificar mediante tablas de verdad las leyes de De Morgan. Dibujar los circuitos
10_Para las siguientes funciones dar el circuitos y la tabla de verdad
11_ Armar el circuitos utilizando circuitos integrados de la familia TTL
F = A' . B + A . B'
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